Computer Org. & Architecture

EE 4243
Computer Org. & Architecture
The objective of this homework is to test your understanding of designing, implementing, and testing
4X1 MUX using Verilog coding. Due date of the homework is: Saturday, June 18
th, 2022, 11:59pm.
20 points will be penalized for submissions after 11:59pm on Saturday, June 18
th, 2022, and any
submission after 11:59pm Sunday, June 19
th, 2022, will not be graded.
You have to upload a scanned version of your solutions on Blackboard. If you don’t have a scanner
around you, you can use Cam Scanner—a mobile app that scans images in a neat way, as if they’re
scanned through a copier. The report should be a single file with the codes and the timing chart.
For questions related to the Lab, please email Wasim (email: wasim.dipon@my.utsa.edu).
1. Write the Verilog code for main module and test bench for a 4X1 MUX. (You can copy paste in
the report document)
2. Write few lines about the operation of the MUX and provide a block diagram and Truth table of
4X1 MUX
3. Include the screen shot of the Verilog codes, both the source code and the test bench code.
4. Screenshot of timing chart that pops up after running behavioral simulation.
Lab Assignment # 1
Summer 2022
June 13, 2021

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